Track: Research Track |
| Stable Implementation of Voice Activity Detector Using Zero-Phase Zero Frequency Resonator on FPGA |
| Voice Activity Detection (VAD) is a crucial signal processing technique employed to discern voiced and unvoiced segments within speech signals. Its significance extends to various applications such as Speech Coding, Voice Controlled Systems, and speech feature extraction. In Adaptive multi rate (AMR) speech coding, VAD plays a pivotal role in efficiently coding diverse speech frames at varying bit rates. In this presentation, we showcase the application of the Zero-Phase Zero Frequency Resonator (ZP-ZFR) as a VAD, specifically implemented on hardware. ZP-ZFR, characterized by its Infinite Impulse Response (IIR) filter nature, offers the distinct advantage of requiring a lower filter order, rendering it suitable for hardware implementation. Our proposed system's focal point is its implementation using TIMIT database, utilizing the Nexys Video Artix-7 FPGA board. The implementation journey unfolds through Vivado 2021.1, a widely recognized tool in FPGA development, with Verilog as the chosen Hardware Description Language (HDL). By presenting this research on hardware, we contribute a versatile solution that holds potential across various applications. Our presentation aims to encapsulate the essence of our work, highlighting the efficacy of ZP-ZFR in VAD and its seamless integration within hardware environments. |
|
| Presentation Video |
| Presentation Notes |
| Syed_Stable-Implementation-of-Voice-Activity-Detector-Using-Zero-Phase-Zero-Frequency-Resonator-on-FPGA.pdf |
